1. Field of the Invention
This invention relates to a FIFO buffer for interfacing between two system buses and, more particularly, to a buffer for interfacing between an I/O bus of a computer workstation and an internal bus of a graphics adapter.
2. Description of the Related Art
Data or information in computers is processed in a predominantly serial fashion. Many times there are sources and destinations of data that are connected by buses. Usually there is a mismatch in the rate at which data is produced and the rate at which is can be accepted. The data is therefore stored in a first-in-first-out (FIFO) buffer between the data source and data destination to accommodate any mismatches between the rate at which the data source can generate the data and the rate at which the data destination can process it.
One such application for a FIFO buffer is for interfacing between the I/O system bus of a computer or workstation and the internal bus of a graphics adapter coupled to a display device. The buffering requirements are complicated by the fact that, typically, several processes are running concurrently on the workstation processor, each of which may have to access the graphics adapter. Also, in many systems, read access as well as write access to the graphics adapter is required. What is desired, therefore, is a FIFO buffer that can transfer data bidirectionally and can accommodate several processes running simultaneously on the workstation processor.